The final application, On-Board DAta flow Simulator (ODAS), will run on a Data Processing Unit (DPU) emulated by the LEON3 processor qualified for space, foreseen to be used by the future ESA science space missions such Euclid (M-class) and Athena XMS (L-class).
  • Readout electronics (ROEs) simulator:
  • It has the role to receive, amplify and digitize the simulated signal from the detector. The housekeeping (HK) parameters will be also acquired internally.

  • Data Processing Unit (DPU):
  • It controls all the FLSW components by distributing low level telecomand (TCs) and collecting and monitoring the HK parameters. The DPU also collects the uncompressed raw science data, pre-process them and perform the data lossless compression.

  • Instrument Control Unit (ICU) simulator:
  • It hosts the algorithms for instrument control. It sends TCs and receives HK.

  • Mass Memory Unit (MM-U):
  • It receives the compressed science data packets.
A fast and reliable simulator of the raw science data produced by the IR detector will be also implemented. The simulations will correspond to the NISP instrument technical specifications and to the realistic properties of the expected observational data. We will also implement realistic simulation of the slow control data flow.

The simulations will be in accordance with the Euclid technical specifications and ESA and ECSS standards.

ODAS will be the first FLSW application to be developed for the LEON3 processor. Its technical implementation implies the use of commercially available components only. Our application will test for the first time the LEON3 symmetric and asymmetric multiprocessing characteristics under RTEMS (Real Time Executive for Multiprocessor System) operating system. ODAS will have the potentiality to be adapted and used by the future satellites or micro-satellites carrying complex instruments. The ODAS compliance to ESA and ECSS standards will be ensured by the rigid application of the prescriptions.

We consider the TRL=2 at the beginning of the project. This is motivated by the fact that the basic concepts and structure of the algorithms to be developed in the project are already understood and have been applied in different other space missions (e.g. Planck, XMM-Newton). We foresee at the end of the project to reach TRL=6. At that time, ODAS will be operational on the LEON3 processor with simulated connections to the spacecraft control system and to the on-board simulated instrument. The developed software and the used hardware will be compliant to the applicable ESA and ECSS standards.

The expertise to be acquired by the project team will be applicable to any FLSW application based on ESA and ECSS standards and will allow the team to participate to future ESA announcements of opportunity, including those for optional programs to which Romania adhered or will adhere.
  • Generation of Simulated Input Data

  • We will simulate raw science input data, corresponding to Euclid/NISP instrument technical specifications (in terms of spatial resolution, image depths, properties of the expected observational data) and simulations of the slow control (TC+HK) data flows between DPU, ROEs, ICU and MM-U in accordance with the Euclid technical specifications and ESA and ECSS standards.

  • ODAS product design

  • To start the product design, it is necessary to define the system input/output parameters (e.g. data blocks structure, size, transmission speed, etc.) and the system requirements needed to fulfill its functions. The ODAS product design consists in: flight software (FLSW) design, including test and validation SW, and hardware (HW) design.

  • ODAS Implementation, Test and Validation

  • We will start by developing each dedicated SW package in C / C ++ language that will be then included in a global SW project. We choose to use the open source operating system RTEMS (Real Time Executive for Multiprocessor System) from Gaisler LEON Company. This will allow us to run programs on the LEON3 processor development board GR712RC by using both processors in an efficient and speeding way. In parallel, we will implement the system HW presented in Figure 2 by using the existing LEON3 processor development board GR712RC, complemented by two new purchased SpaceWire interfaces. Source programs developed in previous phases will be compiled and linked, obtaining the object code that will be introduced in GR712RC-LEON3 system by using an auxiliary library, GRMON, provided by Aeroflex Gaisler-GR712RC with the development board.