The following results are expected to be delivered within the OANA project:
- An optimized version of the INA library written in MATLAB and adapted for onboard analysis of data, the first step towards the onboard application (TRL 3).
- An optimized version of INA library translated into VHDL, the intermediate step towards the final technology (TRL 4).
- A laboratory model of the INA library based on the FPGA technology (TRL 5).
- A feasibility study and guidelines for further development to achieve TRL 6.
The project is divided into the following three stages:
STAGE 1: 07.09.2017 – 31.12.2017
STAGE 2: 01.01.2018 – 31.12.2018
STAGE 3: 01.01.2019 – 07.09.2019